This invention relates to sample and hold circuits and in particular to a fully differential sample and hold adder circuit which is especially useful in analog integrated circuit design.
To avoid the adverse effects of noise in single-ended operational amplifier, it is well-known that a fully differential circuit may be used to avoid such effects and maintain an accurate output. Thus in analog signal processing, fully differential circuits are frequently used. In particular, in conversions between digital and analog signals, fully differential sample and hold circuits have often been used to achieve the conversion and to maintain accurate outputs.
In many applications, it is desirable to be able to add a fully differential signal to a single-ended voltage signal. Single-ended signals, in contrast to fully differential signals, are explained in "Microelectronic Circuits," by Adel S. Sedra and Kenneth C. Smith, published by CBS College Publishing, New York. In conventional fully differential sample and hold circuit design, this is usually accomplished by connecting the single-ended signal through a single-ended to fully differential converter and an adder circuit. When such configuration is implemented in integrated circuits, the above-described design requires considerable area in the semiconductor medium while its accuracy is less than ideal. The additional circuit required for such design, in addition to extra silicon area, reduces the speed of the circuit, which may cause difficulties for certain applications. It is therefore desirable to provide an improved fully differential sample and hold circuit which permits the addition of a single-ended signal and a fully-differential signal where the above-described difficulties are not present.